This application claims the benefit of a Japanese Patent Application No. 11-264430 filed Sep. 17, 1999, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to magnetic memories, and more particularly to a ferromagnetic random access memory and a memory cell array using the same.
The random access memory is essential for use as a main storage of an information processing apparatus such as a computer. Conventionally, the random access memory is formed by a semiconductor memory device such as a DRAM, but it is possible to form the random access memory by a magnetic random access memory using magnetoresistance. The magnetic random access memory has a simple structure in which a nonmagnetic layer made of an insulator or a conductor is sandwiched between a pair of ferromagnetic layers, and this simple structure enables miniaturization to suit integration. Generally, such a magnetic random access memory is nonvolatile and has a good response characteristic. Accordingly, the magnetic random access memory is regarded as being suited for use as a memory of an ultra high-speed computer which will be developed in the future. For example, the magnetic random access memory is described in Parkin et al., xe2x80x9cExchange-biased magnetic tunnel junctions and application to nonvolatile magnetic random access memory (invited)xe2x80x9d, Journal of Applied Physics, Vol. 85, No. 8, pp.5828-5833, Apr. 15, 1999.
2. Description of the Related Art
FIG. 1 is a diagram showing the structure of a conventional magnetic random access memory using a ferromagnetic tunnel junction proposed in Parkin et al.
In a magnetic random access memory (MRAM) 10 shown in FIG. 1, a pinning layer 11 which is made of an antiferromagnetic material is formed on a word line (pattern) WL which extends in a row direction, and a pinned layer 12 which is made of a ferromagnetic material is formed on the pinning layer 11. In the ferromagnetic pinned layer 12, a magnetization direction is fixed, that is, pinned, in a direction of an arrow, by the antiferromagnetic pinning layer 11 provided thereunder. Furthermore, a nonmagnetic tunnel insulator layer 13 and a free layer 14 which is made of a ferromagnetic material are successively formed on the ferromagnetic pinned layer 12, and a bit line (pattern) BL which extends in a column direction is formed on the ferromagnetic free layer 14. The ferromagnetic free layer 14 is magnetized in a direction indicated by an arrow or, in an opposite direction, by a combined magnetic field which is formed by a write current which flows through the word line WL and the bit line BL. In other words, in the MRAM 10, information is written in the form of the magnetization of the ferromagnetic free layer 14.
On the other hand, a magnetoresistance of a ferromagnetic tunnel junction formed by the ferromagnetic pinned layer 12, the ferromagnetic free layer 14 and the nonmagnetic tunnel insulator layer 13 interposed therebetween is used when reading the information written in the MRAM 10.
More particularly, spin polarization is generated within conduction electrons within a ferromagnetic layer such as the ferromagnetic free layer 14 and the ferromagnetic pinned layer 12, and the number of up-spin electrons and the number of down-spin electrons differ. In a case where the magnetization directions of the ferromagnetic free layer 14 and the ferromagnetic pinned layer 12 are parallel, the up-spin electrons or the down-pin electrons within the ferromagnetic free layer 14 can tunnel through the nonmagnetic tunnel insulator layer 13 at a vacancy level of the electrons existing within the ferromagnetic pinned layer 12 and having a corresponding spin state, and the ferromagnetic tunnel junction has a low resistance. On the other hand, in a case where the magnetization directions of the ferromagnetic free layer 14 and the ferromagnetic pinned layer 12 are antiparallel, a vacancy level corresponding to the up-spin electrons or the down-spin electrons within the ferromagnetic free layer 14 does not exist within the ferromagnetic pinned layer 12, and for this reason, the tunneling of the electrons does not occur within the nonmagnetic tunnel insulator layer 13. In other words, when the ferromagnetic free layer 14 and the ferromagnetic pinned layer 12 are magnetically antiparallel, the ferromagnetic tunnel junction has a large resistance.
Accordingly, in the MRAM 10 shown in FIG. 1, it is possible to read the information written in the ferromagnetic free layer 14 by detecting a voltage across the word line WL and the bit line BL. The information which is written within the ferromagnetic free layer 14 in the form of the magnetization is held even if a power supply is turned OFF, and as a result, the MRAM 10 forms a nonvolatile memory. In addition, the magnetization of the ferromagnetic free layer 14 will not be reversed even if the resistance is detected, and a nondestructive read can be made from the MRAM 10.
On the other hand, when the MRAM 10 shown in FIG. 1 is further miniaturized, a ratio of the surface area with respect to the volume of the magnetic material increases, and due to the effects of a closure magnetic field which is generated by the magnetization of the ferromagnetic free layer 14 or the ferromagnetic pinned layer 12 as shown in FIG. 2A, magnetic domains are generated in the ferromagnetic free layer 14 or the ferromagnetic pinned layer 12 as shown in FIG. 2B. When such magnetic domains are generated, an apparent magnetization as a whole is lost, and the ferromagnetic tunnel junction cannot operate.
In order to avoid this problem, it is necessary to use a material having a large coercivity for the ferromagnetic pinned layer 12 or the ferromagnetic free layer 14. However, a large current is required to write the information if such a material having the large coercivity is used for the ferromagnetic pinned layer 12 or the ferromagnetic free layer 14. For example, in order to generate a magnetic field on the order of approximately 10 Oe which is required to reverse the magnetization by a current supplied to the word line WL which is formed at a position 100 nm from the MRAM 10 shown in FIG. 1, for example, it is necessary to use a current on the order of several mA. However, when such a large current is supplied to the word line WL which is formed by a 0.1 xcexcm rule, a current density becomes on the order of 107 A/cm2.
On the other hand, a conventional MRAM shown in FIG. 3 which is suited for miniaturization is proposed in a U.S. Pat. No. 5,477,482.
A spin valve MRAM 20 shown in FIG. 3 has a stacked structure similar to that of the MRAM 10 shown in FIG. 1. The spin valve MRAM 20 shown in FIG. 3 includes a disk-shaped antiferrromagnetic pinning layer 21 formed on a word line (pattern) WL, a disk-shaped ferromagnetic pinned layer 22 formed on the pinning layer 21, a ring-shaped ferromagnetic free layer 24 formed above the ferromagnetic pinned layer 22, and a non-magnetic conductor layer 23 interposed between the ferromagnetic pinned layer 22 and the ferromagnetic free layer 24. A bit line (pattern) BL is formed on the ferromagnetic free layer 24, in a direction intersecting the word line (pattern) WL. In this spin valve MRAM, a magnetoresistance observed between the word line (pattern) WL and the bit line (pattern) BL changes depending on the magnetization direction of the ferromagnetic free layer 24, as a result of the scattering which is dependent upon the direction of the spin of the electrons generated at an interface of the ferromagnetic pinned layer 22 and the nonmagnetic conductor layer 23 and at an interface of the nonmagnetic conductor layer 23 and the ferromagnetic free layer 24.
According to the spin valve MRAM 20 having the structure shown in FIG. 3, the ferromagnetic pinned layer 22 and the ferromagnetic free layer 24 both have the disk shape. Hence, when the ferromagnetic pinned layer 22 and the ferromagnetic free layer 24 are magnetized along the circumferential direction clockwise or counterclockwise, the direction of the closure magnetic field matches the magnetization direction, and the magnetic domains described above in conjunction with FIG. 2 will not be formed even when the spin valve MRAM 20 is miniaturized.
On the other hand, according to the spin valve MRAM 20 shown in FIG. 3, the ferromagnetic pinned layer 22, the ferromagnetic free layer 24, the antiferromagnetic pinning layer 21 and the nonmagnetic conductor layer 23 are all conductor layers. For this reason, a resistance between the bit line BL and the word line WL is small, and there is a problem in that a large current becomes necessary in order to detect the magnetoresistance when reading the written information.
Moreover, in the spin valve MRAM 20 shown in FIG. 3, there is a problem in that it is difficult to set the magnetization of the ferromagnetic pinned layer 22 in a desired circumferential direction. In other words, since the antiferromagnetic pinning layer 21 is formed with respect to the entire lower main surface of the ferromagnetic pinned layer 22, the magnetization direction is simply fixed in one direction when the magnetization direction of the ferromagnetic pinned layer 22 is fixed by the magnetization of the antiferromagnetic pinning layer 21 in a state where an external magnetic field is applied on the spin valve MRAM 20. Consequently, the magnetization of the ferromagnetic pinned layer 22 cannot be made along the desired circumferential direction.
Accordingly, it is a general object of the present invention to provide a novel and useful ferromagnetic tunnel junction random access memory, spin valve random access memory, single ferromagnetic layer random access memory, and memory cell array using the same, in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a ferromagnetic tunnel junction random access memory, spin valve random access memory, single ferromagnetic layer random access memory, and memory cell array using the same, which are suited for miniaturization, easy to produce, and display a large change in resistance.
Still another object of the present invention is to provide a ferromagnetic tunnel junction random access memory comprising: a ferromagnetic tunnel junction structure including a first ferromagnetic layer, a second ferromagnetic layer disposed adjacent to the first ferromagnetic layer and having a fixed magnetization, and a tunnel insulator layer interposed between the first and second ferromagnetic layers; a conductor plug penetrating the first ferromagnetic layer, the tunnel insulator layer and the second ferromagnetic layer along a center axis; a first selection line coupled to a first end of the conductor plug; and a second selection line coupled to a second end of the conductor plug opposite to the first end, the first ferromagnetic layer having a generally ring shape surrounding the conductor plug and being insulated from the conductor plug, one of the first and second ferromagnetic layers having an antiferromagnetic layer pattern on a portion thereof. According to the ferromagnetic tunnel junction random access memory of the present invention, a pinning layer which fixes the magnetization direction of a pinned layer is formed not on the entire surface of the pinned layer but only on a portion thereof, so that the magnetization direction of the pinned layer can be set in a circumferential direction which surrounds a write current path penetrating a ferromagnetic tunnel junction. Hence, the magnetization direction of the pinned layer can be set in the clockwise or counterclockwise direction with respect to the write current, thereby enabling miniaturization to an extent which was conventionally impossible due to the effects of the closure magnetic field. In addition, when using the ferromagnetic tunnel junction, the resistance of the memory increases due to the effects of the tunnel insulator layer, and as a result, the write current and the read current can be reduced to enable reduction in the power consumption of the memory.
A further object of the present invention is to provide a ferromagnetic tunnel junction random access memory comprising: a ferromagnetic tunnel junction structure including a first ferromagnetic layer, a second ferromagnetic layer disposed adjacent to the first ferromagnetic layer and having a fixed magnetization, and a tunnel insulator layer interposed between the first and second ferromagnetic layers; a conductor plug penetrating the first ferromagnetic layer, the tunnel insulator layer and the second ferromagnetic layer along a center axis; a first selection line coupled to a first end of the conductor plug; and a second selection line coupled to a second end of the conductor plug opposite to the first end, the first ferromagnetic layer having a generally ring shape surrounding the conductor plug and being insulated from the conductor plug, one of the first and second ferromagnetic layers having a coercivity larger than that of the other of the first and second ferromagnetic layers. According to the ferromagnetic tunnel junction random access memory of the present invention, a pinning layer which fixes the magnetization direction of a pinned layer is formed not on the entire surface of the pinned layer but only on a portion thereof, so that the magnetization direction of the pinned layer can be set in a circumferential direction which surrounds a write current path penetrating a ferromagnetic tunnel junction. Hence, the magnetization direction of the pinned layer can be set in the clockwise or counterclockwise direction with respect to the write current, thereby enabling miniaturization to an extent which was conventionally impossible due to the effects of the closure magnetic field. In addition, when using the ferromagnetic tunnel junction, the resistance of the memory increases due to the effects of the tunnel insulator layer, and as a result, the write current and the read current can be reduced to enable reduction in the power consumption of the memory.
Another object of the present invention is to provide a spin valve random access memory comprising: a spin valve junction structure including a first ferromagnetic layer, a second ferromagnetic layer disposed adjacent to the first ferromagnetic layer and having a fixed magnetization, and a nonmagnetic conductor layer interposed between the first and second ferromagnetic layers; a conductor plug extending along a center axis within the spin valve junction structure by penetrating the first ferromagnetic layer, the nonmagnetic conductor layer and the second ferromagnetic layer; a first selection line coupled to a first end of the conductor plug; a second selection line coupled to a second end of the conductor plug opposite to the first end; a third selection line coupled to a first position on a sidewall surface of the spin valve junction structure; and a fourth selection line coupled to a second position on the sidewall surface of the spin valve junction structure confronting to the first position, the first ferromagnetic layer having a generally ring shape surrounding the conductor plug and being insulated from the conductor plug, one of the first and second ferromagnetic layers having an antiferromagnetic layer pattern disposed thereon. According to the spin valve random access memory of the present invention, a pinning layer which fixes the magnetization direction of a pinned layer is formed not on the entire surface of the pinned layer but only on a portion thereof, so that the magnetization direction of the pinned layer can be set in a circumferential direction which surrounds a write current path penetrating a ferromagnetic tunnel junction. Hence, the magnetization direction of the pinned layer can be set in the clockwise or counterclockwise direction with respect to the write current, thereby enabling miniaturization to an extent which was conventionally impossible due to the effects of the closure magnetic field. In addition, when using the spin valve junction, a current path during a read operation mode is formed parallel to the surface of the ferromagnetic layer, and as a result, it is possible to prevent the power consumption of the memory from becoming large due to an excessively small resistance as was the case of the conventional spin valve random access memory which forms a current path perpendicularly to the ferromagnetic layer.
Still another object of the present invention is to provide a spin valve random access memory comprising: a spin valve junction structure including a first ferromagnetic layer, a second ferromagnetic layer disposed adjacent to the first ferromagnetic layer and having a fixed magnetization, and a nonmagnetic conductor layer interposed between the first and second ferromagnetic layers; a conductor plug extending along a center axis within the spin valve junction structure by penetrating the first ferromagnetic layer, the nonmagnetic conductor layer and the second ferromagnetic layer; a first selection line coupled to a first end of the conductor plug; a second selection line coupled to a second end of the conductor plug opposite to the first end; a third selection line coupled to a first position on a sidewall surface of the spin valve junction structure; and a fourth selection line coupled to a second position on the sidewall surface of the spin valve junction structure confronting to the first position, the first ferromagnetic layer having a generally ring shape surrounding the conductor plug and being insulated from the conductor plug, one of the first and second ferromagnetic layers having a coercivity larger than that of the other of the first and second ferromagnetic layers. According to the spin valve random access memory of the present invention, a pinning layer which fixes the magnetization direction of a pinned layer is formed not on the entire surface of the pinned layer but only on a portion thereof, so that the magnetization direction of the pinned layer can be set in a circumferential direction which surrounds a write current path penetrating a ferromagnetic tunnel junction. Hence, the magnetization direction of the pinned layer can be set in the clockwise or counterclockwise direction with respect to the write current, thereby enabling miniaturization to an extent which was conventionally impossible due to the effects of the closure magnetic field. In addition, when using the spin valve junction, a current path during a read operation mode is formed parallel to the surface of the ferromagnetic layer, and as a result, it is possible to prevent the power consumption of the memory from becoming large due to an excessively small resistance as was the case of the conventional spin valve random access memory which forms a current path perpendicularly to the ferromagnetic layer.
A further object of the present invention is to provide a single ferromagnetic layer random access memory comprising: a ferromagnetic layer; a conductor plug penetrating a central portion of the ferromagnetic layer; a first selection line coupled to a first end of the conductor plug; and a second selection line coupled to a second end of the conductor plug opposite to the first end, the ferromagnetic layer having a generally ring shape surrounding the conductor plug and being insulated from the conductor plug. According to the single ferromagnetic layer random access memory of the present invention, the structure is extremely simple and the number of selection lines can be minimized. Hence, the single ferromagnetic layer random access memory is suited for improving the integration density of a memory cell array which uses memory cells made up of such a single ferromagnetic layer random access memory.
Another object of the present invention is to provide a memory cell array comprising: memory cells disposed in a matrix arrangement, each of the memory cells comprising a ferromagnetic tunnel junction random access memory comprising: a ferromagnetic tunnel junction structure including a first ferromagnetic layer, a second ferromagnetic layer disposed adjacent to the first ferromagnetic layer and having a fixed magnetization, and a tunnel insulator layer interposed between the first and second ferromagnetic layers; a conductor plug penetrating the first ferromagnetic layer, the tunnel insulator layer and the second ferromagnetic layer along a center axis; a first selection line coupled to a first end of the conductor plug; a second selection line coupled to a second end of the conductor plug opposite to the first end; and a third selection line disposed on and electrically connected to the first ferromagnetic layer at a position avoiding the conductor plug, the first ferromagnetic layer having a generally ring shape surrounding the conductor plug and being insulated from the conductor plug, one of the first and second ferromagnetic layers having an antiferromagnetic layer pattern on a portion thereof or, having a coercivity larger than the other of the first and second ferromagnetic layers, the second selection line comprising a conductor pattern which electrically connects the second end of the conductor plug and the second ferromagnetic layer; a first common selection line extending in a first direction within the memory cell array; a second common selection line extending in the first direction within the memory cell array in parallel to the first common selection line; a third common selection line extending in a second direction different from the first direction within the memory cell array; and a switch coupled between the third common selection line and the second selection line with respect to each of the memory cells, a first group of memory cells arranged in the first direction having the first selection line coupled to the first common selection line and the third selection line coupled to the second common selection line, a second group of memory cells arranged in the second direction having the second selection line coupled to the third common selection line. According to the memory cell array of the present invention, it is possible to supply a write current and a read current to only a selected memory cell by simply providing a switch such as a transistor with respect to each of the memory cells.
Still another object of the present invention is to provide a memory cell array comprising: memory cells disposed in a matrix arrangement, each of the memory cells comprising a first diode, a second diode, and a ferromagnetic tunnel junction random access memory comprising: a ferromagnetic tunnel junction structure including a first ferromagnetic layer, a second ferromagnetic layer disposed adjacent to the first ferromagnetic layer and having a fixed magnetization, and a tunnel insulator layer interposed between the first and second ferromagnetic layers; a conductor plug penetrating the first ferromagnetic layer, the tunnel insulator layer and the second ferromagnetic layer along a center axis; a first selection line coupled to a first end of the conductor plug; a second selection line coupled to a second end of the conductor plug opposite to the first end; a third selection line disposed on and electrically connected to the first ferromagnetic layer at a position avoiding the conductor plug; and a fourth selection line disposed on and electrically connected to the second ferromagnetic layer at a position avoiding the conductor plug, the first ferromagnetic layer having a generally ring shape surrounding the conductor plug and being insulated from the conductor plug, one of the first and second ferromagnetic layers having an antiferromagnetic layer pattern on a portion thereof or, having a coercivity larger than the other of the first and second ferromagnetic layers, a first common selection line extending in a first direction within the memory cell array; a second common selection line extending in the a second direction different from the first direction within the memory cell array; a switch coupled between the third common selection line and the second selection line with respect to each of the memory cells, a first group of memory cells arranged in the first direction having the second and fourth selection lines coupled to the second common selection line, a second group of memory cells arranged in the second direction having the second selection line coupled to the third common selection line, the first diode being coupled between the second common selection line and the second selection line, the second diode being coupled between the second common selection line and the fourth selection line, the first and second diodes having mutually different characteristics. According to the memory cell array of the present invention, it is possible to supply a write current and a read current to only a selected memory cell by simply providing a nonlinear element such as a diode with respect to each of the memory cells.
A further object of the present invention is to provide a memory cell array comprising: memory cells disposed in a matrix arrangement, each of the memory cells comprising a first diode, a second diode, and a spin valve random access memory comprising: a spin valve junction structure including a first ferromagnetic layer, a second ferromagnetic layer disposed adjacent to the first ferromagnetic layer and having a fixed magnetization, and a nonmagnetic conductor layer interposed between the first and second ferromagnetic layers; a conductor plug extending along a center axis within the spin valve junction structure by penetrating the first ferromagnetic layer, the nonmagnetic conductor layer and the second ferromagnetic layer; a first selection line coupled to a first end of the conductor plug; a second selection line coupled to a second end of the conductor plug opposite to the first end; a third selection line coupled to a first position on a sidewall surface of the spin valve junction structure; and a fourth selection line coupled to a second position on the sidewall surface of the spin valve junction structure confronting to the first position, the first ferromagnetic layer having a generally ring shape surrounding the conductor plug and being insulated from the conductor plug, one of the first and second ferromagnetic layers having an antiferromagnetic layer pattern disposed thereon; a first common selection line extending in a first direction within the memory cell array; and a second common selection line extending in a second direction different from the first direction within the memory cell array, a first group of memory cells arranged in the first direction having the first and third selection lines coupled to the first common selection line, a second group of memory cells arranged in the second direction having the second and fourth selection lines coupled to the second common selection line, the first diode being coupled between the second common selection line and the second selection line, the second diode being coupled between the second common selection line and the fourth selection line, the first and second diodes having mutually different characteristics. According to the memory cell array of the present invention, it is possible to supply a write current and a read current to only a selected memory cell by simply providing a nonlinear element such as a diode with respect to each of the memory cells.
Another object of the present invention is to provide a memory cell array comprising: memory cells disposed in a matrix arrangement, each of the memory cells comprising a diode, and a single ferromagnetic layer random access memory comprising: a ferromagnetic layer; a conductor plug penetrating a central portion of the ferromagnetic layer; a first selection line coupled to a first end of the conductor plug; and a second selection line coupled to a second end of the conductor plug opposite to the first end, the ferromagnetic layer having a generally ring shape surrounding the conductor plug and being insulated from the conductor plug; a first common selection line extending in a first direction within the memory cell array; and a second common selection line extending in a second direction different from the first direction within the memory cell array, a first group of memory cells arranged in the first direction having the first selection line coupled to the first common selection line, a second group of memory cells arranged in the second direction having the second selection line coupled to the second common selection line, the diode being coupled between the second common selection line and the second selection line. According to the memory cell array of the present invention, it is possible to supply a write current and a read current to only a selected memory cell by simply providing a transistor or a nonlinear element such as a diode with respect to each of the memory cells.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.